Referenced Approximation Technique for a Rom-Less Sweep Frequency Synthesizer
نویسندگان
چکیده
منابع مشابه
A ROM-Less Direct Digital Frequency Synthesizer Based on Hybrid Polynomial Approximation
In this paper, a novel design approach for a phase to sinusoid amplitude converter (PSAC) has been investigated. Two segments have been used to approximate the first sine quadrant. A first linear segment is used to fit the region near the zero point, while a second fourth-order parabolic segment is used to approximate the rest of the sine curve. The phase sample, where the polynomial changed, w...
متن کاملA ROM-Less Direct Digital Frequency Synthesizer Based on Bezier Curve Approximation
This paper describes the design and implementation of a ROM-Less Direct Digital Frequency Synthesizer (DDS) using Bezier curve approximation. With Bezier curve approximation, phase values between 0 to π are mapped to sine amplitudes. Then, half wave symmetry of sine wave is exploited to construct full sine wave. The proposed approximation introduces maximum error of 7.9×10, which is equivalent ...
متن کاملDesign of a ROM-Less Direct Digital Frequency Synthesizer on FPGA
DDFS (Direct Digital Frequency Synthesizer) is a new technique of frequency synthesizes which introduces the advanced digital processing theory into frequency synthesis. A direct digital frequency synthesizer is composed of a phase accumulator, an adder, an ROM for wave pattern saving, a D/A converter and a LPF (low pass filter). With the rapid development of VLSI, the speed of algorithm is req...
متن کاملA 100-MHz 8-mW ROM-Less Quadrature Direct Digital Frequency Synthesizer
A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed techni...
متن کاملDesign and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA
This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Electrical and Computer Engineering (IJECE)
سال: 2016
ISSN: 2088-8708,2088-8708
DOI: 10.11591/ijece.v6i3.pp1213-1222